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Research Papers

An Embedded System for a High-Speed Manipulator With Single Time Scale Visual Servoing

[+] Author and Article Information
Migara H. Liyanage

Faculty of Engineering and Applied Science,
Department of Mechanical Engineering,
Memorial University of Newfoundland,
St. John's, NL A1B 3X9, Canada
e-mail: mhl545@mun.ca

Nicholas Krouglicof

Professor
School of Sustainable Design Engineering,
University of Prince Edward Island,
Charlottetown, PE C1A 4P3, Canada
e-mail: nkrouglicof@upei.ca

1Corresponding author.

Contributed by the Dynamic Systems Division of ASME for publication in the JOURNAL OF DYNAMIC SYSTEMS, MEASUREMENT, AND CONTROL. Manuscript received April 12, 2016; final manuscript received January 5, 2017; published online May 10, 2017. Assoc. Editor: Heikki Handroos.

J. Dyn. Sys., Meas., Control 139(7), 071007 (May 10, 2017) (10 pages) Paper No: DS-16-1182; doi: 10.1115/1.4035740 History: Received April 12, 2016; Revised January 05, 2017

This study presents the development of an embedded system for controlling a high-speed robotic manipulator. Three different types of controllers including hardware proportional derivative (PD), software PD, and single time scale visual servoing are considered in this study. Novel field programmable gate array (FPGA) technology was used for implementing the embedded system for faster execution speeds and parallelism. It is comprised of dedicated hardware and software modules for obtaining sensor feedback and control signal (CT) estimation, providing the control signal to the servovalves. A NIOS II virtual soft processor system was configured in the FPGA for implementing functions that are computationally expensive and difficult to implement in hardware. Quadrature decoding, serial peripheral interface (SPI) input and output modules, and control signal estimation in some cases was carried out using the dedicated hardware modules. The experiments show that the proposed controller performed satisfactory control of the end effector position. It performed single time scale visual servoing with control signal updates at 330 Hz to control the end effector trajectory at speeds of up to 0.8 ms−1. The FPGA technology also provided a more compact single chip implementation of the controller.

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Figures

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Fig. 2

A schematic diagram of the proposed single time scale visual servoing controller architecture

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Fig. 1

Proposed high-speed visual servoing system

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Fig. 3

FPGA implementation of the proposed controller

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Fig. 4

Edge detection circuitry for quadrature decoding

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Fig. 11

Structure of the FPGA with the NIOS II processor

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Fig. 12

The schematic of the Hardware PD controller

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Fig. 9

The schematic of the timing diagram of multiple SPI/Out for servovalve driver circuit

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Fig. 10

The servovalve driver operational amplifier circuit

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Fig. 14

The performance of the controller implemented using hardware and NIOS processor

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Fig. 15

The response of θ1 to a step input from −15 deg to +15 deg (the units of KP1 and KP2 are in bits/pulse)

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Fig. 16

The response of θ2 to a step input from −15 deg to +15 deg (the units of KP1 and KP2 are in bits/pulse)

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Fig. 17

Position of end effector in workspace with the high-speed camera and encoders as feedback

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Fig. 18

Position of the end effector in workspace for PD and visual servoing controllers

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Fig. 5

The schematic diagram of the position sensitive detector (PSD)

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Fig. 6

The schematic of the timing diagram of ADS8320 chip

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Fig. 7

The schematic of the timing diagram of Multiple SPI/In interface for the high-speed optical position sensor

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Fig. 8

The schematic of the timing diagram of Max 541 DAC chip

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Fig. 13

Speed of obtaining 100 encoder readings and a position reading as feedback

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