Abstract

Package level thermal performance of flip-chip plastic ball grid array (FC-PBGA) packages has been predicted using experimentally validated mechanistic methodologies. The resulting conjugate heat transfer models have been solved using methods of computational fluid dynamics under natural and forced convection for freestream velocities up to 2 m/s. Overall junction to ambient, Θja, junction-to-board, Ψjb, and junction to case Ψ thermal resistances (here after referred to as thermal parameters) have been derived from the results of these computations. Using these models and methodologies, which are previously validated against experimental data, a parametric study of effect of die size on the package thermal parameters has been carried out for die sizes in the range 2 to 20 mm (area of 4–400 mm2) under natural and forced convection with freestream velocities in the range of 0.5 to 2 m/s. The predictions in this study are expected to be ±10% of the measured data. Based on this work the following conclusions have been drawn:

1. The junction to ambient, Θja, and junction to board, Ψjb, thermal resistances decrease with increase in freestream velocity, U, and junction to case thermal resistance, Ψ, increases with U. Ψjb shows a weaker dependence on U than Θja does.

2. For a fixed substrate size, package thermal resistances, Θja and Ψjb, decrease as the die size increases from 2 mm (4 mm2) to 20 mm (400 mm2). However, these resistances reach asymptotic values for die sizes above 50 mm2. The change in these resistances is in the range 20% to 35% and the effect of freestream velocity on the percentage changes is small.

3. An extensive database of experimentally validated FC-PBGA package thermal parameters have been generated for a wide range of die sizes.

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